Verification Undergraduate Student (R0) per el Barcelona Supercomputing Center

BSC is constructing a full RISC-V ecosystem, from the design of the processors to the tape-out of them; also, BSC is working in the full software stack.

Applications are invited for an undergraduate student to contribute to the verification of RISC-V High Performance Computing (HPC) architectures at the Barcelona Supercomputing Center (BSC). BSC intends to pave the way to the future low-power European processor for Exascale in the context of multiple architecture initiatives (EPI, Lenovo, Intel, etc.).

Key Duties

• Define functional coverage at the ISA, interface and microarchitectural levels, incorporating them into an existing verification environment.
• Collect, analyze and improve coverage results, developing and adapting tests and testbenches for that end.
• Document the coverage plan.
• Debug failing tests in the verification environment.

Data de tancament: Dissabte, 16 Desembre, 2023

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