BSC has an open position for a Junior Engineer/ Research Engineer/ Researcher in the Computer Sciences Department to be a part of an active Computer Architecture research group working on design and development of an out-of-order processor as part of a hardware accelerator in an HPC platform.
Key Duties
- Research of computer architectural techniques and development of RTL hardware structures related to superscalar OoO core design to improve the efficiency, scalability, and performance of a current RISC-V core generator
- Review and analyze the state-of-the-art performance techniques for OoO processor architectures to identify the most effective approaches.
- Design RTL structures implementing the selected techniques for RISC-V Core architectures
- Integration into RISC-V Core Generator: This integration should provide an efficient and configurable means of generating RISC-V processor cores with the new capabilities, demonstrating a tradeoff balance of performance improvements.
- Verification and Validation: Develop a verification framework in CoCoTB for the derived modules of the core optimizations. Implement verification tests and validation procedures to ensure the correctness and functionality of the generated processor cores with the newly added features.
- Performance Evaluation: Evaluate the impact of the new capabilities on the generated RISC-V processor cores through extensive simulation and benchmarking. Measure the improvements in terms of execution efficiency, reduced cycle count, and overall performance.
Data de tancament: Dimecres, 31 Gener, 2024
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