Undergraduate student - RTL engineering on an out-of-order processor per el Barcelona Supercomputing Center

BSC is constructing a full RISCV ecosystem, from the design of the processors to the tape-out of them; also, BSC is working in the full software stack.

In this context, BSC has to develop an HPC out-of-order vector RISCV processor. This vacancy is for 4 undergraduate students for this processor.

Key Duties

You will use your design expertise to design and build complex digital designs focused on OoO processors, vector units and uncore

You will collaborate closely with design architects and verification engineers and perform hands-on design, writing RTL code.

Design integration, logic synthesis and design optimization for area, timing and power.

Participating in chip bring-up and testing.

Simulate and program simulators to research on the behaviour of the architecture

Termini per aplicar: Dilluns, 31 Octubre, 2022

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