Research Engineer - RTL Integration (RE3-T1) per al Barcelona Supercomputing Center

Applications are invited for an engineer in High Performance Computing (HPC) architectures at the Barcelona Supercomputing Center (BSC). BSC intends to pave the way to the future low-power European processor for Exascale in the context of multiple architecture initiatives, such as EPI, Lenovo, Intel and Zettascale Lab.

Key Duties

• As an engineer on the Integration team, you will collaborate with a research team to develop, implement, and verify an HPC system based on RISC-V. Your role will involve working on cutting-edge device architectures, defining designs, implementing solutions, and conducting verification, as well as creating essential hardware and software components for system simulation and debugging.
• Design and Implement the components required to assemble a RISC-V-based HPC system that meets the specified performance targets, including on-chip peripherals.
• Analyze the performance of a RISC-V based HPC processor system, with special emphasis on the top-level integration of the constituent modules and the interconnection to external peripherals.
• Lead debugging sessions to resolve integration issues, including compatibility, specification, and performance concerns, and act as a bridge between the customer and BSC engineers by triaging issues and escalating them to the appropriate teams.
• Mentor junior engineers: provide guidance, share expertise, and foster their professional growth to enhance their technical skills and project contributions.

Data de tancament: Divendres, 31 Gener, 2025

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