Research Engineer - Design of a supercomputing processor chip (RE1) per el Barcelona Supercomputing Center

The Barcelona Supercomputing Center (BSC) www.bsc.es is embarking on an umbrella of large-scale projects to design, and manufacture an open-source High Performance Out-of-Order Vector Processing Unit that will serve as the basic building block of BSCs next generation supercomputer, the Marenostrum 6 (MN6) which will be operational in 2028/2029. In this ambitious and potentially rewarding endeavor, we need engineers and computer scientists at all levels of expertise (from 0 to 20+ years) and in both hardware and software fields. The final team will be 100 engineers and scientists.

The applicants would ideally have experience/ambition in at least one or more of the following fields:

• Hardware (Processor architecture, micro-architecture, accelerators, memory hierarchy, memory controllers, HBM, DRAM, non-volatile memory, RTL design, VHDL, verilog, SystemC, System verilog, Synopsys, Cadence, Mentor Graphics, synthesis, place and route, timing closure, packaging, PCB design, verification, validation, CI, post-silicon debug, DFT, gate-level simulation)

• Software (programming models, MPI, compilers, operating systems, managed runtimes, OpenMP, task-based programming models, containers, security, fault-tolerance, virtualization C/C++, Tcl, Python, Perl/Csh )

Key Duties

• Research and RTL

Data de tancament: Divendres, 15 Novembre, 2024

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