The DARE project is a great opportunity to collaborate on the design and implementation of an HPC processor based on the RISC-V ISA. In particular, this job position is related to the design and implementation of the vector unit for the next generation HPC processor. The main objectives are:
- Improvements on the existing microarchitecture to add out of order execution coupled with superscalar instruction issue on the multiple vector functional units.-
- Design and implement the memory interface for the VPU to have direct access to the memory hierarchy
- Evaluate the option to integrate the RISC-V matrix extension on top of the existing vector state
- Performance improvements on the existing microarchitecture
- Propose interesting research idea with the aim of developing research papers for top conferences
Key Duties
- Design and implement advanced features for out of order execution for the vector unit
Data de tancament: Divendres, 31 Gener, 2025
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