Research Engineer 3 for RTL OoO Core Development (RE3) per al Barcelona Supercomputing Center

BSC has an open position for a Research Engineer in the Computer Sciences Department to be a part of an active Computer Architecture research group working on designing and developing a high-end out-of-order processor for the HPC Zettascale Laboratory. We are seeking a highly skilled and experienced Senior RTL Engineer to join our team in maintaining and optimizing a current high-performance Out-of-Order (OoO) CPU. This role involves developing robust, efficient, and scalable RTL implementations for advanced microarchitectural features, contributing to the next generation of cutting-edge processor designs.

As a senior engineer, you will play a pivotal role in shaping our CPU microarchitecture and mentoring team members to ensure the delivery of high-quality designs.

Key Duties

• Research of computer architectural techniques and development of RTL hardware structures related to superscalar OoO core design to improve the efficiency, scalability, and performance of a current RISC-V core.
• Review and analyze the state-of-the-art performance techniques for OoO processor architectures to identify the most effective approaches.
• Design RTL structures by implementing the selected techniques for RISC-V CPU architectures. Implement complex control logic, data paths, and microarchitectural features in SystemVerilog.
• Integration into RISC-V Core: This integration should provide an efficient and configurable means of RISC-V processor cores with the new capabilities, demonstrating a tradeoff balance with performance improvements.
• Verification and Validation: Develop a verification strategy with CoCoTB for the derived modules and Python hardware modeling. Implement verification tests and validation procedures to ensure correctness and functionality.
• Performance Evaluation: Evaluate the impact of the new capabilities on the RISC-V processor core through extensive simulation and benchmarking. Measure the improvements in terms of execution efficiency, reduced cycle count, and overall performance.
• Follow the methodology and quality standards for the code base development.
• Documentation and Reporting: Document design specifications, microarchitecture, and test plans. Prepare reports and presentations on design progress, issues, and performance metrics.
• Tool and Methodology Development: Develop and maintain scripts and tools to automate design and verification tasks. Contribute to the improvement of design and verification methodologies within the team.
• Code Quality and Maintenance: Ensure high-quality, maintainable, and reusable RTL code. Perform code reviews and provide constructive feedback to peers.
• Compliance and Standards: Ensure design compliance with industry standards and best practices. Follow project-specific guidelines and contribute to the establishment of new standards within the team.
• Coordinate high-complexity tasks in applied Computer Architecture Design towards RTL implementation with the team, and collaborate in the planning and strategies for the improvement of the development framework.

Data de tancament: Dilluns, 17 Març, 2025

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