We will research on HW/SW co-design to do matrices multiplication, taken into account the size of the matrices and the sparcity. We will develop the corresponding accelerators and the corresponding instruction set.
Key Duties
- Research and develop a new attached matrix extension, for new algorithms.
- Hardware modeling and performance evaluation using simulation tools with High Performance Computing requirements as part of a team.
- Modify and develop simulators to study different options for the matrix extension
- Create the code to run in the simulator
- HW/SW codesign of algorithms to multiply matrices, for different sizes of the matrices and sparcity.
Data de tancament: Diumenge, 16 Febrer, 2025
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