BSC is looking for talented and motivated professionals with expertise in Design Verification for a chip integrating an European HPC accelerator in the context of the DARE Project and other related research projects. The design is based on RISC-V architecture. BSC contributes a RISC-V vector accelerator to the EPI project and verifying the functional correctness of the chip is key for success.
Key Duties
- You will use your design and verification expertise to verify complex RISC-V digital designs, focused on a system that integrates vector units and scalar processors, and possibly other accelerators. The system integrates all those components together with memory hierarchy and IO interfaces.
- You will collaborate closely with design and verification engineers in active projects and perform hands-on verification, and contribute to design, build, and integrate the designs.
- Using your UVM, SystemVerilog and problem-solving skills, you will build efficient and effective verification environments that exercise processor designs through their corner-cases and expose all types of bugs.
- You will be responsible for the full life cycle of verification, including verification planning, test and assertion implementation, failure triaging, debugging, coverage definition and others.
- You will automatize the processes by creating and maintaining verification & post-processing scripts for verification, triaging, coverage and debugging.
- You will train others in the configuration, deployment, use and/or maintenance of verification software, scripts and workflows.
- You supervise, guide and coordinate the work of less experienced Verification engineers working in the project.
- You will define and implement coverage plans for the design, and analyse the code and functional coverage results obtained to identify verification holes and to show progress towards tape-out.
Data de tancament: Divendres, 31 Gener, 2025
Més posts de Recerca
Cap comentari:
Publica un comentari a l'entrada