BSC Computer Architecture for Parallel Paradigms department is currently offering a research engineer position with a focus on RTL development of a Floating-Point Unit (FPU) for the HPC Digital Autonomy with RISC-V in Europe project or DARE. The DARE objectives are
- Contribute to European technological sovereignty by building a complete software/hardware ecosystem for HPC based on RISC-V, optimized for critical EU HPC applications by using a co-design approach.
- Produce a long-term roadmap with a critical timeline, milestones and all the necessary activities needed to build and deploy post-exascale systems in Europe using European technology.
- Deliver EU-owned, energy-efficient, high-end processors and accelerators designed for industrial-grade HPC and Cloud solutions.
Key Duties
- Design of floating-point arithmetic functional units for HPC and AI systems.
- Area and energy analysis and optimizations.
- Integration of FPU to Scalar Core and Vector Accelerator.
- Resolving bugs and working closely with the verification team to expand and improve the verification environment.
- Collaboration with the physical design team on synthesis experiments.
Data de tancament: Dimecres, 15 Gener, 2025
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